128-Bit Design
The Borealis supports up to
32 MB of on-board 100 MHz
SGRAM. The chip’s 128-bit
core drawing engine can
stretch and bi-linearly interpo-
late 8 pixels per clock cycle,
supporting horizontal/vertical
non-integer zooms in a single
pass. Its performance is rated
at 533 MB/sec. Fully PCI 2.1
compliant.
Memory Resources
Borealis's video frame buffer memory is configured as 16 or 32
MB block of 100 MHz SGRAM, with a 128-bit wide (512K x 128)
data bus. Its video RAM is accessible as a linear buffer via the
memory window’s interface or via the drawing engine. Borealis3
supports simultaneous read/write of 16 pixels of 8-bits, 8 pixels of
16-bits, or 4 pixels of 32-bits.
On-chip Texture Cache:
8 Kbits of on-chip texture cache for bitmaps shared between
adjacent pixels. Removes artifacts and smoothes transitions
between large 2D or 3D images, elements, and textures.
32-Bit Z Buffering:
Stores Z (depth) value for each pixel. Provides automatic hidden
surface removal in the hardware, freeing the CPU and system bus.
Color-space conversion
YUV formatted data is common to NTSC/PAL video (including
DVD). Data acquired from a color decoder (video capture chip)
Borealis Feature Summary
or from the host computer is stored in off-screen memory. It is
then copied to on-screen memory, and during the copy process it
is converted to the current drawing display format (8-, 16-, or 32-
bit). In the process, a color key in the source or target data
space can be used to limit writing of the converted data to specif-
ic pixels. Continual copying/converting of live video to a display
window is the perfect application of the Display List Processor.
Display List Processor
Executes a sequence of commands from memory, enabling the
graphics engine to perform repetitive tasks without using up PCI
bandwidth or CPU resources. This list, which can be modified
and expanded, is stored in local (chip) memory.
Graphics Output
Borealis features a triple 250 MHz 8-bit DAC with a 128-bit mem-
ory interface. It supports 8/16/32 bits per pixel. The integrated
RAMDAC features a X11 compliant cursor hardware generator. Its
translucent cursor enhances graphical user interface functionality.
The cursor pattern is contained in a downloadable 64 x 64 x 2
memory.
Borealis
Technical
Overview
64-bit wide pixel data bus
Fine-grained PLL programming
Large Screen ISO-compliant
refresh rates
Pixel re-synchronization
Direct color
Gamma correction
256-shade gray scale
Triple monotonic 8-bit DACs
100 MHz 8-bit VGA data input
On-chip diagnostics
Power-down modes
Integrated color maps and DAC
The Borealis
Graphics accelerator
The Eclipse3 is powered by the Borealis graphics accelerator,
which is a 128-bit PCI graphics controller. It drives very high res-
olution VGA graphics over an enhanced 128-bit wide local data
bus. It’s designed to draw up to sixteen 256-color pixels to mem-
ory each instruction cycle and can generate many hundreds of
thousands of shaded triangles per second. To increase overall
system throughput, the chip's display list function enables the
host CPU and the Eclipse3 card to process data independently.
Borealis Features
page
4
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji